Analysis of “SystemC” design flow for FPGA implementation

Abstract

High level language termed as SystemC language is recently gaining popularity in VLSI industries especially in Hardware-Software co-design. Using SystemC, Hardware IPs can be modeled at system level which helps to reduce the time to market for SOCs. In most applications SystemC is utilized to verify functionality of the design. However there has been relatively less work done on the synthesis of equivalent hardware from SystemC. In this paper, Finite Impulse Response Filter and Greatest Common divisor are designed as examples in SystemC language and their corresponding synthesis flow from SystemC to FPGA is proposed. The proposed method of synthesis would be time saving than the conventional design and synthesis using HDL in RTL perspective.