Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

Main Article Content

Prof. Parvaneh Basaligheh

Abstract

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

Downloads

Download data is not yet available.

Article Details

How to Cite
Prof. Parvaneh Basaligheh. (2017). Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device. International Journal of New Practices in Management and Engineering, 6(01), 14–19. https://doi.org/10.17762/ijnpme.v6i01.51
Section
Articles