PROF. PARVANEH BASALIGHEH. Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device. International Journal of New Practices in Management and Engineering, [S. l.], v. 6, n. 01, p. 14–19, 2017. DOI: 10.17762/ijnpme.v6i01.51. Disponível em: https://www.ijnpme.org/index.php/IJNPME/article/view/51. Acesso em: 2 may. 2024.